MC33260
http://onsemi.com
12
Pin Numbers are Relevant to the PDIP- -8 Version
Figure 29. PWM Latch
PWM
Latch
R
S
Q
Q
Synchronization
Arrangement
--
+
OVP, UVP
&
--
+
PWM Latch
Comparator
V
control
(V
pin2
-- Regulation Output)
Output
Buffer
7
ZCD & OCP
Current Sense
Comparator
--60 mV
Oscillator Sawtooth
Output_Ctrl
Th--Stdwn
V
CC
5
ALEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
fromPin4anddisablesitduringthe400firstnsofthepower
switchconduction.Thispreventstheblockfromreactingon
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on Pin 4.
PROTECTIONS
OCP (Overcurrent Protection)
Refer to Current Sense Block.
OVP (Overvoltage Protection)
The feedback current (I
o
) is compared to a threshold
current(I
ovpH
).Ifitexceedsthisvalue,thegatedrivesignal
ismaintainedlowuntilthiscurrentgetslowerthanasecond
level (I
ovpL
).
Figure 30. Internal Current Thresholds
Gate
Drive
Enable
V
control
I
o
I
uvp
I
regL
I
ovpH
I
ovpL
I
regH
So, the OVP upper threshold is:
V
ovpH
= V
pin1
+
r
R
o
?I
ovpH
u
where:
R
o
is the feedback resistor that is connected between
Pin 1 and the output voltage,
I
ovpH
is the internal upper OVP current threshold,
V
pin1
is the Pin 1 clamp voltage.
Practically, V
pin1
that is in the range of 2.5 V, can be
neglected. The equation can then be simplified:
V
ovpH
= R
o
(M? ?I
ovpH
(mA) (V)
On the other hand, the OVP low threshold is:
V
ovpL
= V
pin1
+
r
R
o
?I
ovpL
u
where I
ovpL
is the internal low OVP current threshold.
Consequently, V
pin1
being neglected:
V
ovpL
= R
o
(
M?/DIV>
)
?I
ovpL
(
mA
) (
V
)
The OVP hysteresis prevents erratic behavior.
I
ovpL
is guaranteed to be higher than IregH (refer to
parameters specification). This ensures that the OVP
function doesnt interfere with the regulation one.
UVP (Undervoltage Protection)
This function detects when the feedback current is lower
than14%ofI
ref
.Inthiscase,thePWMlatchisresetandthe
power switch is kept off.
This protection is useful to:
?nbsp Protect the preregulator from working in too low
mains conditions.
?nbsp To detect the feedback current absence (in case of a
nonproper connection for instance).
The UVP threshold is:
V
uvp
H V
pin1
+
r
R
o
(M? ?I
uvp
(mA)
u
(V)
Practically (V
pin1
being neglected),
V
uvp
= R
o
(
M?/DIV>
)
?I
uvp
(
mA
) (
V
)
Maximum On- -Time Limitation
As explained in PWM Latch, the maximum on- -time is
accurately controlled.
Pin Protection
All the pins are ESD protected.
发布紧急采购，3分钟左右您将得到回复。
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